Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor memory device which is capable of correcting a phase of a clock used to input and output data according to the number of activated banks.
Semiconductor memory devices are used to store data. When a data processor, such as a memory control unit (MCU), requests data, a semiconductor memory device outputs data corresponding to an address inputted from the data requesting device, or stores data provided from the data requesting device at a position corresponding to the address.
A recently developed high-speed memory device is designed to input/output two data between a rising edge and a falling edge of a system clock, and input/output two data between the falling edge and a next rising edge of the system clock. That is, the memory device is designed to input/output four data in one cycle of the system clock.
However, since the system clock has only two states, i.e., a logic high level and a logic low level, a data clock having two times the frequency of the system clock may be required in order to input/output four data in one cycle of the system clock. That is, the data clock dedicated to data transmission may be required.
For example, a high-speed semiconductor memory device uses a system clock as a reference clock for transmission of an address and a command, and uses a data clock as a reference clock for the data transmission by controlling the data clock to have two times the frequency of the system clock.
That is, the data clock may be controlled to have two cycles within one cycle of the system clock, and the data may be inputted or outputted at a rising edge and a falling edge of the data clock. As such, in the high-speed semiconductor memory device, four data may be inputted or outputted in one cycle of the system clock.
The high-speed semiconductor memory device may input/output data by using two clocks having different frequencies in order for a read or write operation, as opposed to a conventional DDR synchronous memory device which uses one system clock as a reference clock to perform a read or write operation.
However, if the phase of the system clock and the phase of the data clock are not aligned, the reference for the transmission of the command and the address and the reference for the data transmission are not aligned. This means that a high-speed semiconductor memory device may not operate normally.
Therefore, in order to secure a reliable operation of the high-speed semiconductor memory device, an interface training operation must be performed between a semiconductor memory device and a data processor in an initial stage of operation.
The interface training operation refers to an operation in which an interface for transmitting a command, an address, and data is initially trained to operate at an optimized timing before an actual operation is performed between the semiconductor memory device and the data processor.
Such interface training operation includes an address training, a clock alignment training, a read training, and a write training. An operation of aligning the data clock and the system clock is performed in the clock alignment training.
FIG. 1 is a timing diagram illustrating a known write training method.
Referring to FIG. 1, an internal data clock WT SYNC. CLK for receiving a write data in a semiconductor memory device is generated by compensating an external data clock EXTERNAL WCLK for an internal asynchronous delay INTERNAL ASYNC DELAY. The internal asynchronous delay INTERNAL ASYNC DELAY is caused in a path through which the external data clock EXTERNAL WCLK is transferred inside the semiconductor memory device. The internal asynchronous delay may be a value which varies depending on pressure, voltage, and temperature (PVT) variations. Therefore, the value may not be previously determined, and instead is determined through the write training.
When the semiconductor memory device is supplied with power and starts its operations, a semiconductor memory device controller and the semiconductor memory device perform the write training. Through the write training, an optimum input timing of a write data may be obtained by delaying the write data based on the external data clock EXTERNAL WCLK. After finding the optimum input timing of the write data WRITE DATA through the write training, the semiconductor memory device controller starts to transmit the write data WRITE DATA to the semiconductor memory device. When the write data WRITE DATA is inputted at the optimum input timing, a sufficient setup hold time based on the internal data clock WT SYNC. CLK is obtained.
FIG. 2 is a timing diagram illustrating a known read training method.
An internal data clock RD SYNC. CLK is used in the semiconductor memory device controller in order to receive a read data from the semiconductor memory device. The internal data clock RD SYNC. CLK is generated by compensating the external data clock EXTERNAL WCLK for an internal asynchronous delay INTERNAL ASYNC DELAY. The internal asynchronous delay INTERNAL ASYNC DELAY is caused in a path through which the external data clock EXTERNAL WCLK is transferred inside the semiconductor memory device. The internal asynchronous delay INTERNAL ASYNC DELAY is a value which varies depending on pressure, voltage, and temperature (PVT) variations. Therefore, the value cannot be previously determined, and instead is determined through a read training.
When the semiconductor memory device is supplied with power and starts its operations, the semiconductor memory device controller and the semiconductor memory device perform the read training. The read training is an operation to find an optimum timing of generating a read strobe signal GPU READ STROBE based on the external data clock EXTERNAL WCLK. The read strobe signal GPU READ STROBE determines a valid window of the read data based on the internal data clock RD SYNC. CLK. After finding the optimum timing of generating the read strobe signal GPU READ STROBE, the semiconductor memory device starts to read the read data outputted from the semiconductor memory device controller. Meanwhile, in the case of a semiconductor memory device including a plurality of banks, a total current consumption of the semiconductor memory device changes according to the number of banks activated among the plurality of banks. Accordingly, a level of a voltage used in the semiconductor memory device may change.
For example, as the number of banks activated among the plurality of banks increases, the total current consumption of the semiconductor memory device increases. Accordingly, the level of the voltage used in the semiconductor memory device may decrease. On the contrary, as the number of banks activated among the plurality of banks decreases, the total current consumption of the semiconductor memory device decreases. Accordingly, the level of the voltage used in the semiconductor memory device may increase.
When the current amount and the voltage level used in the semiconductor memory device changes, a clock delay, which may be applied to an external data clock EXTERNAL WCLK in order to generate optimum read/write internal data clocks RD/WT SYNC. CLK through the write training and the read training at the initial stage of operation of the semiconductor memory device, may also change. Therefore, a sufficient setup/hold time may not be ensured at a window period of a write data, and a position of a strobe signal, which may determine an optimal value in a window period of a read data, may be undesirably shifted.